1. Field of the Invention
The present invention relates in general to metal-oxide-semiconductor (MOS) memories and manufacturing method therefor, and relates in particular to a semiconductor memory cell section suitable for use in Dynamic Random Access Memory (DRAM) devices and a manufacturing method therefor.
2. Description of the Related Art
In semiconductor memory devices such as DRAM, it is usual to utilize n-type MOS (NMOS) transistors in a memory array section (memory cell transistor) while the transistors in the peripheral circuit sections (logic circuit transistors) utilize a combination of NMOS and p-type MOS (PMOS) transistors, i.e., complementary metal oxide semiconductor (CMOS) transistor. Conventionally, NMOS transistors for use in both memory array section and the peripheral circuit section have been based on a transistors structure having both an n-type high concentration region and an n-type low concentration region in the source and drain diffusion layers, the so-called lightly-doped drain (LDD) structure which is made by a same fabrication process.
In recent years, however, it has come to be recognized that crystal defects produced during the ion implantation process for making the n-type high concentration region of memory cell transistors can no longer be ignored. For this reason, the low concentration in an n-type region has been achieved in the memory array section by using the same process conditions during the ion implantation process as those used for making n-type low concentration regions in logic circuit transistors. As for the memory cell transistors, the n-type source and drain diffusion layers have been produced using only the low concentration region.
As mentioned in a reference in IEEE ("The impact of N.sup.- drain length and gate-drain/source overlap on submicrometer LDD devices for VLSI", IEEE ELECTRON DEVICE LETTERS, VOL. EDL-8, NO.10, OCTOBER 1987), the LDD structure in an n-type low concentration region is usually produced by implanting phosphorous (P.sup.+)ions in a dose range of 1.times.10.sup.12 .about.4.times.10.sup.13 ions/cm.sup.2 at about 40 KeV. The junction depth of the n-type low concentration region produced by this process is about 0.05 .mu.m, and inevitably, the source and drain diffusion layers of the n-type transistors in the memory cell transistors likewise have shallow diffusion layers.
An adverse consequence regarding the capacitors in the semiconductor memory devices, such as DRAM, is that it is necessary to retain a certain degree of capacitance even if the cell size is diminished. This requirement resulted in the frequent use of capacitors having a three-dimensional architecture so as to obtain an increased effective surface area, for example, by stacking capacitors on a substrate (stacked capacitor). A conventional structure of the stacked capacitor is disclosed, for example, in a U.S. Pat. No. 5,017,982 ("CAPACITOR IN SEMICONDUCTOR DEVICE"), which makes use of arsenic(As) implantation in storage electrode film for the purpose of increasing the electrical conductivity of the storage electrode.
It should be noted, however, that shallow regions of a semiconductor memory structure, such as the regions of 0.05 .mu.m depth from the surface of the substrate, are prone to having many crystal defects originating from various structural damages produced during processing of the memory devices. For this reason, the source and drain diffusion layers in memory cell transistors having shallow junction depth are susceptible to the adverse effects from the crystal defects, leading typically to a problem of low charge retention time of the capacitors caused by the generation of junction leakage current. This effect can be illustrated in terms of the distribution of the refresh times for a plurality of memory cells as shown in FIGS. 6A, 6B. It can be seen in these figures that the refresh times which depend on the capability of each of the memory cell to retain a memory (charge) are skewed broadly towards low refresh time (Tref), thus indicating a loss in reliability of the memory device.